MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 265

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

the e300 core, are caused by instructions. A system management interrupt is an implementation-specific
interrupt. The interrupt classes are shown in
Although interrupts have other characteristics, such as whether they are maskable, the distinctions shown
in
synchronous, imprecise instructions. While the PowerPC architecture supports imprecise handling of
floating-point exceptions, the core implements floating-point exception modes as precise.
The e300 core interrupts and exception conditions that cause them are listed in
Freescale Semiconductor
Reserved
System reset
Machine check
DSI
ISI
Interrupt Type
Table 7-7
define categories of interrupts that the core handles uniquely. Note that
Asynchronous, nonmaskable
Asynchronous, maskable
Synchronous
Synchronous/Asynchronous
00000
00100
00200
00300
00400
Vector Offset
(hex)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Caused by the assertion of either hreset.
Caused by the assertion of the tea signal during a data bus transaction, assertion of mcp ,
an address or data parity error, or an instruction or data cache parity error. Note that the
e300 has SRR1 register values that are different from the G2/G2_LE cores’ when a
machine check occurs.
1
4
6
9
Caused when an instruction fetch cannot be performed for any of the following reasons:
Determined by the bit settings in the DSISR, listed as follows:
• The effective (logical) address cannot be translated. That is, there is a page fault for this
• The fetch access violates memory protection (indicated by SRR1[4] set). If the key bits
portion of the translation, so an ISI interrupt must be taken to load the PTE (and possibly
the page) into memory.
(Ks and Kp) in the segment register and the PP bits in the PTE are set to prohibit read
access, instructions cannot be fetched from this location.
Set if the translation of an attempted access is not found in the primary hash table entry
group (HTEG), or in the rehashed secondary HTEG, or in the range of a DBAT register;
otherwise cleared
Set if a memory access is not permitted by the page or DBAT protection mechanism;
otherwise cleared
Set for a store operation and cleared for a load operation
Set if a data address breakpoint interrupt occurs when the data [0–28] in the DABR or
DABR2 matches the next data access (load or store instruction) to complete in the
completion unit. The different breakpoints are enabled as follows:
• Write breakpoints enabled when DABR[30] is set
• Read breakpoints enabled when DABR[31] is set
Table 7-8. Exceptions and Interrupts
Table 7-7. Interrupt Classifications
Precise/Imprecise
Table
Imprecise
Precise
Precise
7-7.
Exception Conditions
Machine check
System reset
External interrupt
Decrementer
System management interrupt
Critical interrupt
Instruction-caused interrupts
—
Interrupt Type
Table
e300 Processor Core Overview
Table 7-7
7-8.
includes no
7-33