MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 25

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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12-1
Freescale Semiconductor
LCSn Signal Selection ........................................................................................................ 10-78
LBS Signal Selection .......................................................................................................... 10-78
UPM Read Access Data Sampling...................................................................................... 10-80
Effect of LUPWAIT Signal ................................................................................................. 10-81
GPCM Address Timings ..................................................................................................... 10-82
GPCM Data Timings........................................................................................................... 10-83
Interface to Different Port-Size Devices ............................................................................. 10-83
Single-Beat Read Access to FPM DRAM .......................................................................... 10-89
Single-Beat Write Access to FPM DRAM ......................................................................... 10-91
Burst Read Access to FPM DRAM Using LOOP (Two Beats).......................................... 10-93
Refresh Cycle (CBR) to FPM DRAM ................................................................................ 10-95
Exception Cycle .................................................................................................................. 10-96
Interface to ZBT SRAM ..................................................................................................... 10-98
System Connection of the eSDHC........................................................................................ 11-1
eSDHC Block Diagram......................................................................................................... 11-2
DMA System Address Register (DSADDR) ........................................................................ 11-6
Block Attributes Register (BLKATTR) ................................................................................ 11-6
Command Argument Register (CMDARG) ......................................................................... 11-7
Transfer Type Register (XFERTYP)..................................................................................... 11-8
Command Response 0–3 Register (CMDRSPn) .................................................................11-11
Buffer Data Port Register (DATPORT) .............................................................................. 11-13
Present State Register (PRSSTAT)...................................................................................... 11-13
Protocol Control Register (PROCTL)................................................................................. 11-17
System Control Register (SYSCTL)................................................................................... 11-20
Interrupt Status Register (IRQSTAT) .................................................................................. 11-24
Interrupt Status Enable Register (IRQSTATEN) ................................................................ 11-28
Interrupt Signal Enable Register (IRQSIGEN)................................................................... 11-30
Auto CMD12 Error Status Register (AUTOC12ERR) ....................................................... 11-32
Host Capabilities Register (HOSTCAPBLT)...................................................................... 11-34
Watermark Level Register (WML) ..................................................................................... 11-35
Force Event Register (FEVT) ............................................................................................. 11-36
Host Controller Version Register (HOSTVER) .................................................................. 11-37
eSDHC Buffer Scheme ....................................................................................................... 11-38
Example of Dividing a Large Data Transfer ....................................................................... 11-40
DMA CSB Interface Block ................................................................................................. 11-41
Command CRC Shift Register ............................................................................................ 11-42
Two Stages of Clock Divider .............................................................................................. 11-43
a) Card Interrupt Scheme; b) Card Interrupt Detection and Handling Procedure .............. 11-45
Flow Diagram for Card Detection ...................................................................................... 11-47
Flow Chart for Reset of eSDHC and SD I/O Card ............................................................. 11-48
DMA Block Diagram............................................................................................................ 12-1
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
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