MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 804

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
Table 14-78
14.4.6.5
PEX_PM_TIMER, shown in
power management states.
The fields of the PEX_PM_TIMER are described in
14-66
Offset 0x450
Reset 0
Offset 0x440
31–6
Reset 0
31–24
23–12 L1_WAIT_PERIOD Wait period (in PCI Express controller core clock cycles) before entering L1 power state after all
Bits
5–0
11–0
Bits
W
R
W
R
31
31
CLKRN
0
L0s_TIME_IN
0
Name
—
describes the PEX_GCLK_RATIO fields.
Figure 14-81. PCI Express Power Management Timer Register (PEX_PM_TIMER)
0
Name
PCI Express Power Management Timer Register (PEX_PM_TIMER)
0
—
Figure 14-80. PCI Express Core Clock Ratio Register (PEX_GCLK_RATIO)
0
0
—
0
0
Reserved
Clock Ratio Numerator. The numerator of the ratio of the actual PCI Express controller core clock used
to the maximal core clock of 125 MHz. These bits should be programmed only when the PCI Express
controller is required to run at a clock frequency other than the maximum.
The denominator of the ratio is fixed at 16. The default value of this register is 0x10 (16 decimal), which
corresponds to a ratio of 1:1 (or 16/16). For example, if the PCI Express controller clock is 62 MHz, the
ratio of the clocks is 1:2 (equivalent to 8/16). Therefore these bits should be programmed to a value of
8, or 0x0000_0008.
0
0
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Reserved
functions are in a non-D0 power state. The value is calculated as:
Time (in µsec) × PCI Express controller core clock frequency (in MHz)
The time value must be less than 2 µsec
Time in value (in PCI Express controller core clock cycles) for entering L0s power state. The
value is calculated as:
Time (in µsec) × PCI Express controller core clock frequency (in MHz)
The maximum time value is 7 µsec
0
0
Table 14-78. PEX_GCLK_RATIO Fields Description
24 23
0
0
Table 14-79. PEX_PM_TIMER Fields Description
Figure
0
0
0
0
14-81, is used to program the time-in values for entering L0s and L1
0
0
0
0
L1_WAIT_PERIOD
0
1
—
0
0
0
1
0
Table
0
0
0
Description
0
14-79.
Description
1
0
1
0
12 11
0
0
0
0
0
0
1
0
1
L0s_TIME_IN
0
1
Freescale Semiconductor
0
6
1
0
5
1
1
0
Access: Mixed
CLKRN
Access: Mixed
0
0
0
1
0
0 0
0
0
0