MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 891

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.4.1
Table 16-2
standard, 2000 edition. Input signals not used are internally disabled. Except for TSECn_GTX_CLK,
output signals not used are driven low.
Freescale Semiconductor
TSEC_TMR_ALARM1 1588—Alarm out 1
TSEC_TMR_ALARM2 1588—Alarm out 2
TSEC_TMR_TRIG2
TSEC n _TMR_RX_
TSEC n _TMR_TX_
TSEC_TMR_PP1
TSEC_TMR_PP2
TSEC_TMR_PP3
TSEC n _CRS
TSEC n _COL
Signal Name
Signal
ESFD
ESFD
is a description of the eTSEC interface signals. All other modes follow the IEEE 802.3
Detailed Signal Descriptions
For more information on RGMII mode, see Hewlett-Packard Reduced
Gigabit Media-Independent Interface (RGMII) Specification, Version 1.2a,
Dated 9/22/2000.
Table 16-1. eTSEC n Network Interface Signal Properties (continued)
I/O
1588—Trigger in 2
External timer trigger input 2. This is an asynchronous general purpose input (chip external
input pin).
1588—Pulse out 1
Timer pulse per period 1. It is phase aligned with 1588 timer clock (chip external output pin).
1588—Pulse out 2
Timer pulse per period 2. It is phase aligned with 1588 timer clock (chip external output pin).
1588—Pulse out 3
Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external output pin).
1588—Receive external start of frame delimiter
1588—Transmit external start of frame delimiter
I
I
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 16-2. eTSEC Signals—Detailed Signal Descriptions
Collision input. The behavior of this signal is not specified while in full-duplex mode.
Carrier sense input. This signal is not used in the RGMII mode.
Meaning
Meaning
Timing Asserted/Negated—This signal is not required to transition synchronously with
Timing Asserted/Negated—This signal is not required to transition synchronously with
State
State
Asserted/Negated—In MII mode, this signal is asserted upon detection of a collision,
This signal is not used in the RGMII mode.
Asserted/Negated—In MII mode, TSEC n _CRS is asserted while the transmit or
and must remain asserted while the collision persists.
TSEC n _TX_CLK or TSEC n _RX_CLK.
receive medium is not idle. In the event of a collision, TSEC n _CRS must remain
asserted for the duration of the collision.
TSEC n _TX_CLK or TSEC n _RX_CLK.
NOTE
Function
Description
Enhanced Three-Speed Ethernet Controllers
Reset
State
—
—
—
0
0
0
0
0
16-7