MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 190

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Configuration
5.5.5
The PIT programmable register map occupies 32 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All PIT registers are 32 bits wide and reside on 32-bit address boundaries and should only be accessed as
32-bit quantities.
All addresses used in this chapter are offsets from PIT base, as defined in
Table 5-47
5.5.5.1
The periodic interval timer control register (PTCNR), shown in
PIT functions. The register can be read at any time.
Table 5-48
5-48
0x014–0x01F
0–23
Bits
Offset 0x00
Reset
24
Offset
0x00C
0x000
0x004
0x008
0x010
W
R
0
Name
CLEN
—
shows the PIT memory map.
defines the bit fields of PTCNR.
PIT Memory Map/Register Definition
Periodic Interval Timer Control Register (PTCNR)
Periodic interval timer control register (PTCNR)
Periodic interval timer load register (PTLDR)
Periodic interval timer prescale register (PTPSR)
Periodic interval timer counter register (PTCTR)
Periodic interval timer event register (PTEVR)
Reserved
Write reserved, read = 0
Clock enable control bit. Controls the counting of the PIT. When the PIT’s clock is disabled, the counter
maintains its old value. When the counter’s clock is enabled, it continues counting using the previous value.
0 Disable counter.
1 Enable counter.
Figure 5-36. Periodic Interval Timer Control Register (PTCNR)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Periodic Interval Timer (PIT)—Block Base Address 0x0_0400
Table 5-47. PIT Register Address Map
Register
Table 5-48. PTCNR Bit Settings
—
All zeros
Description
Figure
Access
R/W
R/W
R/W
w1c
—
R
5-36, is used to enable the different
23
Chapter 3, “Memory Map.”
CLEN CLIN
24
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset Value
—
25
Freescale Semiconductor
26
Access: Read/Write
—
5.5.5.1/5-48
5.5.5.2/5-49
5.5.5.3/5-49
5.5.5.4/5-50
5.5.5.5/5-50
Section/
Page
30
PIM
31