MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 385

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 10-2
Freescale Semiconductor
LOE/LGPL2/
LSRCID[0:4]
LCS[0:3]
LD[0:15]
LFWE0/
LA[0:25]
LGPL0/
LGPL1/
LFCLE
Signal
LWE0/
LWE1/
LFALE
LBCTL
LCLK0
LDVAL
LBS0,
LFRE
Name
LBS1
shows the detailed external signal descriptions for the eLBC.
I/O
O
O
O
O
O
Function(s)
Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions
Alternate
Chip selects. Four chip selects are provided that are mutually exclusive.
GPCM write enable 0/FCM write enable/UPM byte select 0. These signals select or validate each byte
lane of the data bus. For an 8-bit port size, bit 0 is the only defined signal. The least-significant address
bits of each access also determine which byte lanes are considered valid for a given data transfer.
General purpose line 0/FCM command latch enable.
General-purpose line 1/FCM address latch enable.
GPCM output enable/General-purpose line 2/FCM read enable.
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—See
—
—
—
—
—
—
State
State
State
State
State
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 10-1. Signal Properties—Summary (continued)
Asserted/Negated—Used to enable specific memory devices or peripherals connected to the
Asserted/Negated—For GPCM operation, LWE[0:1] assert for each byte lane enabled for
Asserted/Negated—In UPM mode, LGPL0 is one of six general purpose signals; it is driven
Asserted/Negated—In UPM mode, LGPL1 is one of six general purpose signals; it is driven
Asserted/Negated—Controls the output buffer of memory when accessing memory/devices in
eLBC debug
eLBC debug
eLBC. LCS[0:3] are provided on a per-bank basis with LCS0 corresponding to the chip
select for memory bank 0, which has the memory type and attributes defined by BR0 and
OR0.
writing.
LFWE0 enables command, address, and data writes to NAND Flash EEPROMs
controlled by FCM.
LBS[0:1] are programmable byte-select signals in UPM mode. See
“RAM
for details regarding the timing of LWE[0:1].
with a value programmed into the UPM array.
In FCM mode, LFCLE enables command cycles to NAND Flash EEPROMs.
with a value programmed into the UPM array.
In FCM mode, LFALE enables address cycles to NAND Flash EPROMs.
GPCM mode.
In UPM mode, LGPL2 is one of six general purpose signals; it is driven with a value
programmed into the UPM array.
LFRE enables data read cycles from NAND Flash EEPROMs controlled by FCM.
Mode
—
—
—
—
Array,” for programming details about LBS[0:1].
Data buffer control
Non-multiplexed address bus
Data bus
Local bus clocks
Local bus data valid
Local bus source ID
Section 10.4.2, “General-Purpose Chip-Select Machine
Descriptions
Description
Signals
No. of
Enhanced Local Bus Controller
26
16
1
1
1
5
Section 10.4.4.4,
I/O
I/O
O
O
O
O
O
Reset State
(Outputs)
(GPCM),”
Driven
10-5