MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 862

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
a memory read from the mailbox data register and read the message. The following steps are required in
order to use the outbound mailbox mechanism.
14.6.3.2
The remote PCI Express RC device uses the inbound mailbox messages to signal the EP local host across
the PCI Express link. The RC performs a memory write and stores the required message in the PCI Express
inbound mailbox data register (PEX_IMBDR) and then initiates an interrupt to the local host by
performing a memory write and setting the READY bit of the PCI Express inbound mailbox control
register (PEX_IMBCR). When the local host detects the interrupt, it can read the message from the
mailbox data register. The following steps are required in order to use the outbound mailbox mechanism.
14-124
1. The RC should set the MSIE bit of the PCI Express MSI message control register (address 0x72 of
2. The EP local host should set the OMBIE bit of the PCI Express host interrupt enable register
3. The EP local host should program the IVEC field of the PCI Express host miscellaneous interrupt
4. The EP local host should program the MBD field of the PCI Express outbound mailbox data
5. The EP local host should set the READY bit of the PCI Express outbound mailbox control register
6. The PCI Express RC, after receiving the MSI will perform a memory read to the EP’s PCI Express
7. The PCI Express RC should perform a memory write to clear the READY bit of the EP’s PCI
8. The EP can repeat steps 3–5 with an appropriate MSI and message data after verifying that the
1. The EP local host should enable PCI Express interrupts by programming the integrated
2. The EP local host should set the IMBIE bit of the CSB system miscellaneous interrupt enable
3. The PCI Express RC should perform a memory write and store the required message in the EP’s
4. The PCI Express RC should perform a memory write and set the READY bit of the EP’s
the configuration space) to enable the generation of MSI.
(PEX_HIER) to enable interrupt generation to the PCI Express (MSI) at the event of setting the
READY bit of the PCI Express outbound mailbox control register (PEX_OMBCR).
vector register (PEX_HMIVR) with an appropriate vector value. This value, along with the value
programmed in the EP’s PCI Express MSI message control register’s MME field determines the
MSI message data sent to the RC. For example, if the MME field has a value of N, then the lower
N bits of the MSI message data are replaced with the lower N bits of the PEX_HMIVR register.
register (PEX_OMBDR) with the message to be read by the PCI Express remote device (user
defined).
(PEX_OMBCR). This will generate an interrupt (MSI) to the PCI Express root complex.
outbound mailbox data register (PEX_OMBDR) and get the message content.
Express outbound mailbox control register (PEX_OMBCR).
PEX_OMBCR[READY] is cleared.
programmable interrupt controller (IPIC).
register (PEX_CSMIER), to allow interrupt at the event of mailbox ready.
PCI Express Inbound Mailbox Data Register (PEX_IMBDR).
PCI Express inbound mailbox control register (PEX_IMBCR). This will issue an interrupt to the
local host.
Inbound Mailbox
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Freescale Semiconductor