MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 112

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.2.1.2
The reset control logic determines the cause of reset, synchronizes it if necessary, and resets the
appropriate internal hardware. Each reset flow has a different impact on the device logic:
The memory controller, system protection logic, interrupt controller, and I/O signals are initialized only
on hard reset. A SRESET causes a high-priority interrupt to the e300 core.
Table 4-4
4-4
Checkstop reset
Software hard reset
•
•
Resets:
PLLs, clocks, and error capture registers
Resets:
DDR controller, LBC, I/O multiplexors,
GTM, PIT, GPIO, system configuration,
and local access windows
Resets other internal logic
Reset configuration words loaded
HRESET driven by SoC
Hard reset to e300 core
High priority interrupt to the e300 core
RTC
Power-on reset has the greatest impact, resetting the entire device, including clock logic and error
capture registers. This does not reset the RTC module. For more information on RTC reset
sequence, see
Hard reset resets the entire device, excluding RTC module, clock logic, and error capture registers.
Name
identifies the reset actions for each reset source.
Reset Actions
Action
Chapter 15, “Real Time Clock (RTC) Module.”
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
If the core enters checkstop state and the checkstop reset is enabled (RMR[CSRE] = 1), the
checkstop reset is asserted. The enabled checkstop event then generates an internal hard reset
sequence.
A hard reset sequence can be initialized by writing to a memory-mapped register (RCR).
Table 4-3. Reset Causes (continued)
Table 4-4. Reset Actions
Power-On Reset
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Description
Software Hard Reset
External Hard Reset
Software Watchdog
Reset Source
Bus Monitor
Checkstop
Yes
Yes
Yes
Yes
Yes
No
No
No
Freescale Semiconductor
SRESET
Yes
No
No
No
No
No
No
No