MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 149

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.1.4.2
The alternate configuration base address register (ALTCBAR) is used to define the base address for an
alternate 1-Mbyte region of configuration space to be used by the boot sequencer. By loading the proper
boot sequencer command in the serial ROM, the base address in the ALTCBAR can be combined with the
20 bits of address offset supplied from the serial ROM to generate a 32-bit address. Thus, by configuring
this register, the boot sequencer has access to the entire memory map, one 1-Mbyte block at a time. See
Section 17.4.5, “Boot Sequencer Mode,”
The alternate configuration base address register is shown in
Table 5-6
5.1.4.3
The LBC local access window n base address registers (LBLAWBAR0–LBLAWBAR3) are shown in
Figure
Freescale Semiconductor
1
12–31
0–11
‘
Bits
The LBLAWBAR0[BASE_ADDR] reset value depends on the reset configuration word high values. See
“LBLAWBAR0[BASE_ADDR] Reset Value,”
Offset 0x08
Offset 0x20, 0x28, 0x30, 0x38
Reset
Reset
Figure 5-4. LBC Local Access Window n Base Address Registers (LBLAWBAR0–LBLAWBAR3)
W
W
R
R
5-4.
BASE_ADDR Identifies the12 most-significant address bits of an alternate base address used for boot sequencer
0
0
defines the bit fields of ALTCBAR.
Name
—
Alternate Configuration Base Address Register (ALTCBAR)
LBC Local Access Window n Base Address Registers
(LBLAWBAR0–LBLAWBAR3)
ALTCBAR is not considered a local access window on its own, so the boot
sequencer must configure one of the other eight local access windows
properly to reach the desired target peripherals.
Figure 5-3. Alternate Configuration Base Address Register (ALTCBAR)
BASE_ADDR
configuration accesses.
Reserved. Write has no effect, read returns 0.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
BASE_ADDR
Table 5-6. ALTCBAR Bit Settings
for a detailed description.
for more information.
11 12
1
NOTE
All zeros
All zeros
Description
Figure
19 20
5-3.
—
—
System Configuration
Section 5.1.4.3.1,
Access: Read/Write
Access: Read/Write
5-7
31
31