MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 628

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
13.5.3.2
DWords 1–8 constitute eight slots of transaction control and status. Each transaction description includes
the following:
The host controller uses the information in each transaction description, plus the endpoint information
contained in the first three DWords of the buffer page pointer list, to execute a transaction on the USB.
Table 13-41
13.5.3.3
DWords 9–15 of an isochronous transaction descriptor are nominally page pointers (4K aligned) to the data
buffer for this transfer descriptor. This data structure requires the associated data buffer to be contiguous
13-50
31–28
27–16
14–12
11–0
Bits
15
•
•
•
Status results field
Transaction length (bytes to send for OUT transactions and bytes received for IN transactions).
Buffer offset. The PG and Transaction n Offset fields are used with the buffer pointer list to
construct the starting buffer address for the transaction.
Transaction n
Transaction n
Length
Status
Name
Offset
shows the iTD transaction status and control fields.
PG
ioc
iTD Transaction Status and Control List
iTD Buffer Page Pointer List (Plus)
Records the status of the transaction executed by the host controller for this slot. This field is a bit
vector with the following encoding:
31 Active. Set by software to enable the execution of an isochronous transaction by the host
30 Data buffer error. Set by the host controller during status update to indicate that the host controller
29 Babble detected. Set by the host controller during status update when” babble” is detected during
28 Transaction error (XactErr). Set by the host controller during status update in the case where the
For an OUT, this field is the number of data bytes the host controller will send during the transaction.
The host controller is not required to update this field to reflect the actual number of bytes transferred
during the transfer. For an IN, the initial value of the endpoint to deliver. During the status update, the
host controller writes back the field is the number of bytes the host expects the number of bytes
successfully received. The value in this register is the actual byte count (for example, 0 zero length
data, 1 one byte, 2 two bytes, etc.). The maximum value this field may contain is 0xC00 (3072).
Interrupt on complete. If this bit is set, it specifies that when this transaction completes, the host
controller should issue an interrupt at the next interrupt threshold.
These bits are set by software to indicate which of the buffer page pointers the offset field in this slot
should be concatenated to produce the starting memory address for this transaction. The valid range
of values for this field is 0 to 6.
This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. This field is
concatenated onto the buffer page pointer indicated in the adjacent PG field to produce the starting
buffer address for this transaction.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
controller. When the transaction associated with this descriptor is completed, the host controller
clears this bit indicating that a transaction for this element should not be executed when it is next
encountered in the schedule.
is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast
enough during transmission (underrun). If an overrun condition occurs, no action is necessary.
the transaction generated by this descriptor.
host did not receive a valid response from the device (Time-out, CRC, Bad PID, etc.). This bit may
only be set for isochronous IN transactions.
Table 13-41. iTD Transaction Status and Control
Description
Freescale Semiconductor