MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 457

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
26–27
Bits
24
25
28
29
30
31
LOOP
Name
EXEN
TODT
LAST
UTA
NA
—
Loop start/end. The first RAM word in the RAM array where LOOP is 1 is recognized as the loop
start word. The next RAM word where LOOP is 1 is the loop end word. RAM words between,
and including the start and end words, are defined as part of the loop. The number of times the
UPM executes this loop is defined in the corresponding loop fields of the M x MR.
0 The current RAM word is not the loop start word or loop end word.
1 The current RAM word is the start or end of a loop.
Exception enable. Allows branching to an exception pattern at the exception start address
(EXS). When an internal bus monitor time-out exception is recognized and EXEN in the RAM
word is set, the UPM branches to the special exception start address (EXS) and begins
operating as the pattern defined there specifies.
The user should provide an exception pattern to negate signals controlled by the UPM in a
controlled fashion. For DRAM control, a handler should negate RAS and CAS to prevent data
corruption. If EXEN = 0, exceptions are ignored by UPM (but not by local bus) and execution
continues. After the UPM branches to the exception start address, it continues reading until the
LAST bit is set in the RAM word.
0 The UPM continues executing the remaining RAM words, ignoring any internal bus monitor
1 The current RAM word allows a branch to the exception pattern after the current cycle if an
Reserved
Next burst address. Determines when the address is incremented during a burst access.
0 The address increment function is disabled.
1 The address is incremented in the next cycle. In conjunction with the BR n [PS], the increment
UPM transfer acknowledge. Indicates assertion of transfer acknowledge in the current cycle.
0 Transfer acknowledge is not asserted in the current cycle.
1 Transfer acknowledge is asserted in the current cycle.
In case of UPM writes, program UTA and LAST in same RAM word.
In case of UPM reads, program UTA and LAST in consecutive or same RAM words.
Turn-on disable timer. The disable timer associated with each UPM allows a minimum time to
be guaranteed between two successive accesses to the same memory bank. This feature is
critical when DRAM requires a RAS precharge time. TODT turns the timer on to prevent another
UPM access to the same bank until the timer expires.The disable timer period is determined in
M x MR[DS n ]. The disable timer does not affect memory accesses to different banks. Note that
TODT must be set together with LAST, otherwise it is ignored.
0 The disable timer is turned off.
1 The disable timer for the current bank is activated preventing a new access to the same bank
Last word. When LAST is read in a RAM word, the current UPM pattern terminates and control
signal timing set in the RAM word is applied to the current (and last) cycle. However, if the
disable timer is activated and the next access is to the same bank, execution of the next UPM
pattern is held off and the control signal values specified in the last word are extended in
duration for the number of clock cycles specified in M x MR[DS n ].
0 The UPM continues executing RAM words.
1 Indicates the last RAM word in the program. The service to the UPM request is done after
In case of UPM writes, program UTA and LAST in same RAM word.
In case of UPM reads, program UTA and LAST in consecutive or same RAM words.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
time-out.
exception condition is detected.
value of LA n is 1 or 2 for port sizes of 8 and 16 bits, respectively.
(when controlled by the UPMs) until the disable timer expires. For example, precharge time.
this cycle concludes.
Table 10-40. RAM Word Field Descriptions (continued)
Description
Enhanced Local Bus Controller
10-77