MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 134

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.5.1.2
The reset configuration word high register (RCWHR) is shown in
Section 4.3.2.2, “Reset Configuration Word High Register (RCWHR).”
4.5.1.3
RSR, shown in
For example, because software watchdog expiration results in a hard reset, SWRS and HRS are all set after
a software watchdog reset. This register returns to its reset value only when power-on reset occurs.
Table 4-25
4-26
1
Address 0x0_0910
16–18
20–23
24–26
4–14
Bits
0–3
The reset value of this field is determined according to the reset configuration input signals CFG_RESET_SOURCE[0:2]
sampled during the reset flow.
15
19
27
Reset
Reset 0
W
W
R
R
16
0
RSTSRC
SWHR
CSHR
Name
defines the reset status register bit fields.
0
BSF
—
—
—
—
—
RSTSRC
Reset Configuration Word High Register (RCWHR)
Reset Status Register (RSR)
18
Figure
0
n
1
SWHR
Reset configuration word source. Reflects the value of CFG_RESET_SOURCE input signal during the
reset flow. See
Reserved, should be cleared.
Boot sequencer fail. If set, indicates that the I
configuration words. Cleared by writing a 1 to it (writing zero has no effect).
Reserved, should be cleared.
Software hard reset. If set, indicates a software hard reset. SWHR is cleared by writing a 1 to it (writing
zero has no effect).
Reserved
Reserved, should be cleared.
Check stop reset status. When the core enters a checkstop state and the checkstop reset is enabled by
the RMR[CSRE], CSRS is set and it remains set until software clears it. CSRS is cleared by writing a 1
to it (writing zero has no effect).
0 No enabled check stop reset event.
1 Enabled check stop reset event.
19
3
0
4-8, captures various reset events in the device. The RSR accumulates reset events.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 4-25. Reset Status Register Field Descriptions
20
4
0
0
Section 4.3.1.1, “Reset Configuration Word Source.”
Figure 4-8. Reset Status Register (RSR)
0
0
—
0
0
23
0
0
24
0
0
Description
2
C boot sequencer has failed while loading the reset
—
—
0
0
Figure 4-4
26
0
0
CSHR
Changing this field has no effect.
27
and described in
0
0
SWR
28
Freescale Semiconductor
S
0
0
Access: User read/write
BMRS
29
0
0
30
—
14
0
0
HRS
BSF
15
31
0
0