MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 650

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
13.6.5
The host controller executes transactions for devices using a simple, shared-memory schedule. The
schedule is comprised of a few data structures, organized into two distinct lists. The data structures are
designed to provide the maximum flexibility required by USB, minimize memory traffic and
hardware/software complexity.
System software maintains two schedules for the host controller: a periodic schedule and an asynchronous
schedule. The root of the periodic schedule is the PERIODICLISTBASE register. See
“Periodic Frame List Base Address Register (PERIODICLISTBASE),”
PERIODICLISTBASE register is the physical memory base address of the periodic frame list. The
periodic frame list is an array of physical memory pointers. The objects referenced from the frame list must
be valid schedule data structures as defined in
if the periodic schedule is enabled (see) then the host controller must execute from the periodic schedule
before executing from the asynchronous schedule. It will only execute from the asynchronous schedule
after it encounters the end of the periodic schedule. The host controller traverses the periodic schedule by
constructing an array offset reference from the PERIODICLISTBASE and the FRINDEX registers (see
Figure
The end of the periodic schedule is identified by a next link pointer of a schedule data structure having its
T-bit set. When the host controller encounters a T-Bit set during a horizontal traversal of the periodic list,
it interprets this as an End-Of-Periodic-List mark. This causes the host controller to cease working on the
periodic schedule and transitions immediately to traversing the asynchronous schedule. Once this
transition is made, the host controller executes from the asynchronous schedule until the end of the
microframe.
When the host controller determines that it is time to execute from the asynchronous list, it uses the
operational register ASYNCLISTADDR to access the asynchronous schedule, as shown in
13-72
31
13-43). It fetches the element and begins traversing the graph of linked schedule data structures.
Schedule Traversal Rules
31
Periodic Frame List Base
Address
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 13-43. Derivation of Pointer into Frame List Array
Periodic Frame List Element
DWord-Aligned
Address
12
Section 13.5, “Host Data Structures.”
13 12
12 11
Frame Index Register
3 2
2 1 0
for more information. The
0
Freescale Semiconductor
In each microframe,
Periodic Frame
Section 13.3.2.6,
List
•
•
•
Figure
13-44.