MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 99
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 99 of 2327
- Download datasheet (17Mb)
Access to the OTP is done through a memory-mapped APBH slave interface. Each of the
32 words is memory-mapped on APBH for the purpose of reading (requires a bank-opening
sequence). Writing to the OTP is done through an address and data interface, where software
provides the OTP word number (one of 32) and a programming mask.
See
1.3.5 External Memory Controller (EMI)
The i.MX28 contains a fully embedded DRAM controller solution including a multi-port
AXI & AHB arbiter, control and PHY. The key features are as follows:
See
Freescale Semiconductor, Inc.
• A 32-bit word is dedicated to controller read and write locking of the various OTP
• Storage of various ROM configuration bits.
• Storage of HAB data.
• Support for DDR2 (1.8 V), LP-DDR1 (1.8 V) and LV-DDR2 (1.5 V) up to 200 MHz
• Support for up to 1024 MB with any combination of DRAMs up to two chip-enables.
• Fully pipelined command, read and write data interfaces to the memory controller.
• Advanced bank look-ahead features for high memory throughput.
• Front-end interface to three AHB ports and one AXI port with optimized buffering for
• A programmable register interface to control memory device parameters.
• Full initialization of memory on memory controller reset.
• Delay-Line for reliable data capture timing across process, temperature and all supported
• Integrated On Device Termination (ODT) for DDR2 applications.
• Supports all levels of power modes for various device types.
regions (copied into a shadow register).
OCOTP Overview
clock rate (400 MHz data-rate).
high-bandwidth capability.
voltage ranges.
Overview
for more information on the EMI.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
for more information.
Chapter 1 Product Overview
99
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