MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1594

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Unified DMA Block Guide
26.2 Unified DMA Block Guide
This section includes an introduction, descriptions of signals, a description of the control
interface, and a functional description.
26.2.1 Introduction
This section includes an overview, description of features, and a description of the modes
of operation.
1594
• Dynamically configurable to support 10/100 Mbps
• Supports full duplex and configurable half duplex operations
• Supports AMD magic packet detection with interrupt for node remote power
• Supports interface to Fast Ethernet Phy devices through Medium independent interface
• Provides 64 bit FIFO interface (transmit and receive)
• When operating in Full Duplex mode, implements automated Pause Frame (802.3 x
• Implements standard flow control mechanism in full duplex operation mode
• In half duplex mode, provides full collision support, including jamming, backoff and
• Support for VLAN tagged frames as per IEEE 802.1Q
• Programmable MAC address
• Multicast and unicast address filtering on receive based on 64 entries hash table thus
• Programmable frame maximum length providing support for any standard or proprietary
• Statistic indicators for frame traffic as well as errors (alignment, CRC error and so on)
• Multiple internal loopback options
• MDIO master interface for PHY device configuration
• Support for all IEEE 1588 frames
• Reference clock can be chosen independently of network speed
• Software programmable precise time stamping of Ingress frames and Egress frames
• Hardware and software controllable timer synchronization
management
(MII) working at 25 MHz and Reduced Medium independent interface (RMII) working
at 50 MHz
31A) generation and termination providing flow control without user application
intervention
automatic retransmission
reducing higher layer processing load
frame length
and pause frames providing for IEEE 802.3 basic and mandatory management
information database (MIB) package and Remote network monitoring (RFC 2819)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.