MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1230

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
14.8.171 DRAM Control Register 182 (HW_DRAM_CTL182)
This is a DRAM configuration register.
Address:
1230
Reset
Reset
MR0_DATA_3
Bit
Bit
W
W
R
R
RSVD2
30 16
Field
Field
RSVD2
RSVD1
31
31
15
0
0
HW_DRAM_CTL182
30
14
0
0
For DDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to
'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL
Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0
should be set to 'b010.For DDR2 memories: The EMI does not support interleaving and therefore the A3 bit
should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state
machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and
therefore the bits A2:A0 should be set to 'b010.
For LPDDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared
to 'b0. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010.
This data will be programmed into the memory register of the DRAM at initialization or when the write_modereg
parameter is set to 'b1.
Always write zeroes to this field.
MRS data to program to memory mode register 0 for chip select 3.
Holds the memory mode register 0 data for chip select X written during memory initialization. Consult the
memory specification for the fields of this mode register.
This parameter correlates to the memory mode register (MR). The use of this parameter varies based on
the memory type connected to this EMI:
For DDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to
'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL
Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0
should be set to 'b010.For DDR2 memories: The EMI does not support interleaving and therefore the A3 bit
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL181 field descriptions (continued)
28
12
0
0
HW_DRAM_CTL182 field descriptions
800E_0000h base + 2D8h offset = 800E_02D8h
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
MR0_DATA_3
MR0_DATA_2
Description
Description
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0