MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1397

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Address:
Re-
19.4.37 Debug Trap Range High Address for AHB Layer 3
The Debug Trap Range High Address Register defines the upper bound for an address range
that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs
within this range. This register applies only to AHB Layer 3.
This register sets the upper address that defines the debug trap function. When this function
is enabled, any active AHB cycle on Layer 3 which accesses this range will trigger an
interrupt to the ARM core.
EXAMPLE
Address:
Re-
19.4.38 Freescale Copyright Identifier Register (HW_DIGCTL_FSL)
Read-only Freescale Copyright Identifier Register.
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
31
31
0
0
ADDR
ADDR
Field
31 0
Field
31 0
30
30
0
0
29
29
0
0
HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW 8001_C000h base + 2E0h offset
= 8001_C2E0h
HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH 8001_C000h base + 2F0h offset
= 8001_C2F0h
(HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH)
28
28
0
0
HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH field descriptions
HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW field descriptions
This field contains the 32-bit lower address for the debug trap range.
This field contains the 32-bit upper address for the debug trap range.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
23
23
0
0
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
ADDR
ADDR
16
16
0
0
15
15
0
0
Description
Description
Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
1397
0
0
0
0