MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1166
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 1166 of 2327
- Download datasheet (17Mb)
Programmable Registers
Address:
1166
Reset
Reset
TDFI_RDDATA_
TDFI_RDDATA_
OBSOLETE
EN_BASE
Bit
Bit
W
W
R
R
RSVD3
RSVD2
31 24
23 20
19 16
15 12
Field
11 8
EN
31
15
0
0
HW_DRAM_CTL70
30
14
0
0
RSVD2
Always write zeroes to this field.
Always write zeroes to this field.
Sets DFI base value for the tRDDATA_EN timing parameter.
Used to adjust the tdfi_rddata_en parameter to account for the desired delay from the read command to the
the read data enable signal. The CAS latency is defined in the caslat parameter.
The dfi_rddata_en signal can only be sent at a minimum of 1 cycle after the read command. If the programmed
value results in a delay less than 1 cycle, this value will be ignored and a delay value of 1 will be used.
'b0000 = Delay from read command to read data enable is equivalent to CAS latency-3.
'b0001 = Delay from read command to read data enable is equivalent to CAS latency-2.
'b0010 = Delay from read command to read data enable is equivalent to CAS latency-1.
'b0011 = Delay from read command to read data enable is equivalent to CAS latency.
'b0100 = Delay from read command to read data enable is equivalent to CAS latency+1.
'b0101 = Delay from read command to read data enable is equivalent to CAS latency+2.
'b0110, etc.
Always write zeroes to this field.
Holds the calculated DFI tRDDATA_EN timing parameter. READ-ONLY
Holds the calculated value of the trddata_en timing parameter. This equation is dependent on the latency
setting for the address / control path of the PHY as set in the phy_ctrl_reg_2 [25] parameter bit.
If phy_ctrl_reg_2 [25] = 0:
If (tdfi_rddata_en_base + rdlat_adj) = 2:
tdfi_rddata_en = reg_dimm_enable
If (tdfi_rddata_en_base + rdlat_adj) > 2:
tdfi_rddata_en = tdfi_rddata_en_base + rdlat_adj + reg_dimm_enable - RDLAT_WIDTH'h3
Values of (tdfi_rddata_en_base + rdlat_adj) < 2 are not supported.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
OBSOLETE
28
12
0
0
800E_0000h base + 118h offset = 800E_0118h
HW_DRAM_CTL70 field descriptions
27
11
0
0
TDFI_RDDATA_EN
26
10
0
0
25
0
0
9
24
0
0
8
Description
23
0
0
7
22
0
0
6
RSVD3
RSVD1
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
TDFI_RDDATA_EN_BASE
19
0
0
3
TDFI_PHY_RDLAT
18
0
0
2
17
0
0
1
16
0
0
0
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