MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2254
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Programmable Registers
37.5.3 HSADC Control Register 2 (HW_HSADC_CTRL2)
The HSADC Control Register 2 specifies analog ADC config bits.
HW_HSADC_CTRL2: 0x020
HW_HSADC_CTRL2_SET: 0x024
HW_HSADC_CTRL2_CLR: 0x028
HW_HSADC_CTRL2_TOG: 0x02C
This register specifies the config bits for analog ADC block.
EXAMPLE
Address:
2254
Reset
INTERRUPT_
INTERRUPT_
OVERFLOW_
INTERRUPT_
ADC_DONE_
INTERRUPT
TIMEOUT_
Bit
W
R
STATUS
STATUS
STATUS
HW_HSADC_CTRL2_WR(0x0000001f);
FIFO_
Field
3
2
1
0
31
0
HW_HSADC_CTRL2
30
0
This bit is set to one upon all the sequences are finished.It is ANDed with its corresponding interrupt enable
bit to request an interrrupt.Can be cleared by INTERRUPT_STATUS_CLR bit.
This bit is set to one upon FIFO overflow occurred.It is ANDed with its corresponding interrupt enable bit to
request an interrupt.Can be cleared by INTERRUPT_STATUS_CLR bit.
This bit is set to one upon timeout occur.It is ANDed with its corresponding interrupt enable bit to request
an interrupt.Can be cleared by INTERRUPT_STATUS_CLR bit.
Set to 1 when an interrupt is raised. Can be cleared by the INTERRUPT_CLR bit.The host CPU can poll
this bit for the polling mode.
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_HSADC_CTRL1 field descriptions (continued)
28
0
8000_2000h base + 20h offset = 8000_2020h
27
0
26
0
25
0
RSRVD1[31:16]
24
0
Description
23
0
22
0
21
0
20
0
Freescale Semiconductor, Inc.
19
0
18
0
17
0
16
0
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