MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 861

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.8.4 System PLL1, USB1 PLL Control Register 1
PLL1 Lock Control Register
The lock count is driven off of xtal. So after the PLL1 is powered on, the PLL1 Lock should
be asserted after 50 us.
EXAMPLE
HW_CLKCTRL_PLL1CTRL1_WR(BF_CLKCTRL_PLL1CTRL1_FORCE_LOCK(1));
Address:
Freescale Semiconductor, Inc.
Reset
Reset
force pll lock
LOCK_COUNT
FORCE_LOCK
Bit
Bit
W
W
RSRVD1
RSRVD1
R
R
29 16
LOCK
Field
16 0
Field
15 0
31
30
LOCK
31
15
0
0
(HW_CLKCTRL_PLL1CTRL1)
HW_CLKCTRL_PLL1CTRL1 8004_0000h base + 30h offset = 8004_0030h
30
14
0
0
Always set to zero (0).
PLL1 Lock bit. 1=PLL1 Locked. 0=PLL1 Unlocked.
Force the PLL1 Lock sequence to start. 1=Enable Force Lock. This bit is not self clearing.
Reserved - Always set to zero (0).
Status of the PLL1 lock count. The PLL1 lock bit will assert when the count reaches 0x4B0. The lock count
is driven off of xtal, so it should be asserted after 50 us.
HW_CLKCTRL_PLL1CTRL0 field descriptions (continued)
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CLKCTRL_PLL1CTRL1 field descriptions
HW_CLKCTRL_PLL1CTRL1_WR(BF_CLKCTRL_PLL1CTRL1_FORCE_LOCK(0));
28
12
0
0
27
11
0
0
26
10
0
0
25
0
0
9
LOCK_COUNT
24
0
0
8
Description
Description
Chapter 10 Clock Generation and Control (CLKCTRL)
23
RSRVD1
0
0
7
22
0
0
6
// force pll lock sequence
21
0
5
0
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
// clear
16
0
0
0
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