MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1532

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
The BUSY signal goes HIGH as soon as data is written to the transmit FIFO (that is, the
FIFO is non-empty) and remains asserted HIGH while data is being transmitted. BUSY is
negated only when the transmit FIFO is empty and the last character has been transmitted
from the shift register, including the stop bits. BUSY can be asserted HIGH even though
the Debug UART might no longer be enabled.
For each sample of data, three readings are taken and the majority value is kept. In the
following paragraphs, the middle sampling point is defined and one sample is taken either
side of it.
24.2.4 Error Bits
Three error bits are stored in bits [10:8] of the receive FIFO and are associated with a
particular character. An additional error indicating an overrun error is stored in bit 11 of
the receive FIFO.
24.2.5 Overrun Bit
The overrun bit is not associated with the character in the receive FIFO. The overrun error
is set when the FIFO is full, and the next character is completely received in the shift register.
The data in the shift register is overwritten, but it is not written into the FIFO. When an
empty location is available in the receive FIFO, and another character is received, the state
of the overrun bit is copied into the receive FIFO along with the received character. The
overrun state is then cleared.
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• When the receiver is idle (UARTRXD continuously 1, in the marking state) and a LOW
• The start bit is valid if UARTRXD is still LOW on the eighth cycle of Baud16, otherwise
• Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error
is detected on the data input (a start bit has been received), the receive counter, with
the clock enabled by Baud16, begins running and data is sampled on the eighth cycle
of that counter in normal UART mode to allow for the shorter logic 0 pulses (half way
through a bit period).
a false start bit is detected and it is ignored. If the start bit was valid, successive data
bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according
to the programmed length of the data characters. The parity bit is then checked, if parity
mode was enabled.
has occurred. When a full word is received, the data is stored in the receive FIFO, with
any error bits associated with that word (see
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 24-1
shows the bit functions of the receive FIFO.
Table
24-1).
Freescale Semiconductor, Inc.