MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 887

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.8.25 Fractional Clock Control Register 1 (HW_CLKCTRL_FRAC1)
The FRAC1 control register provides control for PFD clock generation.
HW_CLKCTRL_FRAC1: 0x1C0
HW_CLKCTRL_FRAC1_SET: 0x1C4
HW_CLKCTRL_FRAC1_CLR: 0x1C8
HW_CLKCTRL_FRAC1_TOG: 0x1CC
This register controls the 9-phase fractional clock dividers. The fractional clock frequencies
are a product of the values in these registers. NOTE: This register can only be addressed
by byte instructions. Addressing word or half-word are not allowed.
EXAMPLE
*((u8 *)(HW_CLKCTRL_FRAC1_ADDR + 1)) = 30;
Freescale Semiconductor, Inc.
CLKGATECPU
CLKGATEEMI
CPU_STABLE
EMI_STABLE
CPUFRAC
EMIFRAC
IO1FRAC
21 16
Field
13 8
5 0
15
14
7
6
This field controls the IO1 clocks fractional divider. The resulting frequency shall be 480 * (18/IO1FRAC)
where IO1FRAC = 18-35.
EMI Clock Gate. If set to 1, the EMI fractional divider clock (reference PLL0 ref_emi) is off (power savings).
0: EMI fractional divider clock is enabled.
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divide should become
stable quickly enough that this field will never need to be used by either device driver or application code.
This value inverts when the new programmed fractional divide value has taken effect. Read this bit, program
the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not
invert when the fractional divider is taken out of or placed into clock-gated state.
This field controls the EMI clock fractional divider. The resulting frequency shall be 480 * (18/EMIFRAC)
where EMIFRAC = 18-35.
CPU Clock Gate. If set to 1, the CPU fractional divider clock (reference PLL0 ref_cpu) is off (power savings).
0: CPU fractional divider clock is enabled.
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divide should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program
the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not
invert when the fractional divider is taken out of or placed into clock-gated state.
This field controls the CPU clock fractional divider. The resulting frequency shall be 480 * (18/CPUFRAC)
where CPUFRAC = 18-35.
HW_CLKCTRL_FRAC0 field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Chapter 10 Clock Generation and Control (CLKCTRL)
887