MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1232
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Programmable Registers
14.8.173 DRAM Control Register 184 (HW_DRAM_CTL184)
This is a DRAM configuration register.
1232
Reset
MR1_DATA_1
MR1_DATA_0
Bit
W
R
RSVD2
RSVD1
30 16
Field
14 0
RSVD1
31
15
15
0
14
0
Always write zeroes to this field.
Data to program into memory mode register 1 for chip select 1.
Holds the memory mode register 1 data for chip select X written during memory initialization. Consult the
memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this EMI:
For DDR1 memories: This parameter correlates to the extended memory mode register (EMR).
For DDR2 memories: This parameter correlates to the extended memory mode register 1 (EMR1). The EMI
does not support additive latency and therefore the A5:A3 bits should be cleared to 'b000.
For LPDDR1 memories: This parameter has no meaning for this memory type.
This data will be programmed into the appropriate memory register of the DRAM at initialization or when
the write_modereg parameter is set to 'b1.
Always write zeroes to this field.
Data to program into memory mode register 1 for chip select 0.
Holds the memory mode register 1 data for chip select X written during memory initialization. Consult the
memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this EMI:
For DDR1 memories: This parameter correlates to the extended memory mode register (EMR).
For DDR2 memories: This parameter correlates to the extended memory mode register 1 (EMR1). The EMI
does not support additive latency and therefore the A5:A3 bits should be cleared to 'b000.
For LPDDR1 memories: This parameter has no meaning for this memory type.
This data will be programmed into the appropriate memory register of the DRAM at initialization or when
the write_modereg parameter is set to 'b1.
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
HW_DRAM_CTL183 field descriptions
11
0
10
0
0
9
0
8
MR1_DATA_0
Description
0
7
0
6
5
0
4
0
Freescale Semiconductor, Inc.
0
3
0
2
0
1
0
0
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