MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1277

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

16.4.2 BCH Decoding for NAND Reads
When a page is read from NAND flash, BCH syndromes will be computed and, if correctable
errors are found, they will be corrected on a per block basis within the NAND page. This
decoding process is fully overlapped with other NAND data reads and with CPU execution.
The BCH decoder flowchart in
decoder. The hardware flow of reading and decoding a 4096-byte page is shown in
16-10.
Freescale Semiconductor, Inc.
• DMA descriptor 2 enables the BCH engine for encoding to begin the initial writing of
• DMA descriptor 3 issues the write commit command byte under CLE to the NAND.
• DMA descriptor 4 waits for the NAND to complete the write commit/transfer by
• DMA descriptor 6 issues a NAND status command byte under "CLE" to check the
• DMA descriptor 7 reads back the NAND status and compares the status with an expected
• DMA descriptor 8 disables the BCH engine and emits a GPMI interrupt to indicate that
the NAND data by specifying where the data and auxiliary payload are coming from
in system memory.
watching the NAND's ready line status. This descriptor relinquishes the NANDLOCK
on the GPMI to enable the other DMA channels to initiate NAND transactions on
different NAND CS lines.
status of the NAND device following the page write.
value. If there are differences, then the DMA processing engine follows an error-handling
DMA descriptor path.
the NAND write has been completed.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 16-9
shows the steps involved in programming the
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
Figure
1277