MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1330

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Behavior During Reset
17.9 Behavior During Reset
A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See
Correct Way to Soft Reset a Block
CLKGATE bit fields.
17.10 Programmable Registers
SSP Hardware Register Format Summary
SSP0 base address is 0x80010000; SSP1 base address is 0x80012000; SSP2 base address
is 0x80014000; SSP3 base address is 0x80016000
1330
8001_00C0
8001_00D0
8001_0000
8001_0010
8001_0020
8001_0030
8001_0040
8001_0050
8001_0060
8001_0070
8001_0080
8001_0090
8001_00A0
8001_00B0
8001_00E0
8001_00F0
8001_0100
8001_0110
8001_0120
Absolute
address
(hex)
SSP Control Register 0 (HW_SSP_CTRL0)
SD/MMC Command Register 0 (HW_SSP_CMD0)
SD/MMC Command Register 1 (HW_SSP_CMD1)
Transfer Count Register (HW_SSP_XFER_SIZE)
SD/MMC BLOCK SIZE and COUNT Register
(HW_SSP_BLOCK_SIZE)
SD/MMC Compare Reference (HW_SSP_COMPREF)
SD/MMC compare mask (HW_SSP_COMPMASK)
SSP Timing Register (HW_SSP_TIMING)
SSP Control Register 1 (HW_SSP_CTRL1)
SSP Data Register (HW_SSP_DATA)
SD/MMC Card Response Register 0 (HW_SSP_SDRESP0)
SD/MMC Card Response Register 1 (HW_SSP_SDRESP1)
SD/MMC Card Response Register 2 (HW_SSP_SDRESP2)
SD/MMC Card Response Register 3 (HW_SSP_SDRESP3)
SD/MMC Double Data Rate Control Register
(HW_SSP_DDR_CTRL)
SD/MMC DLL Control Register (HW_SSP_DLL_CTRL)
SSP Status Register (HW_SSP_STATUS)
SD/MMC DLL Status Register (HW_SSP_DLL_STS)
SSP Debug Register (HW_SSP_DEBUG)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_SSP memory map
for additional information on using the SFTRST and
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Freescale Semiconductor, Inc.
C000_0000h
E000_0020h
Reset value
0000_0000h
0000_0000h
0000_0001h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0080h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
17.10.1/1331
17.10.2/1333
17.10.3/1336
17.10.4/1336
17.10.5/1337
17.10.6/1337
17.10.7/1338
17.10.8/1338
17.10.9/1339
17.10.10/1342
17.10.11/1342
17.10.12/1342
17.10.13/1343
17.10.14/1343
17.10.15/1344
17.10.16/1345
17.10.17/1346
17.10.18/1348
17.10.19/1349
Section/
page