MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 354

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
354
8000_42C0
8000_42D0
8000_4250
8000_4260
8000_4270
8000_4280
8000_4290
8000_42A0
8000_42B0
8000_42E0
8000_42F0
8000_4300
8000_4310
8000_4320
8000_4330
8000_4340
8000_4350
8000_4360
8000_4370
8000_4380
8000_4390
Absolute
address
(hex)
APBH DMA Channel 3 Current Command Address Register
(HW_APBH_CH3_CURCMDAR)
APBH DMA Channel 3 Next Command Address Register
(HW_APBH_CH3_NXTCMDAR)
APBH DMA Channel 3 Command Register
(HW_APBH_CH3_CMD)
APBH DMA Channel 3 Buffer Address Register
(HW_APBH_CH3_BAR)
APBH DMA Channel 3 Semaphore Register
(HW_APBH_CH3_SEMA)
AHB to APBH DMA Channel 3 Debug Information
(HW_APBH_CH3_DEBUG1)
AHB to APBH DMA Channel 3 Debug Information
(HW_APBH_CH3_DEBUG2)
APBH DMA Channel 4 Current Command Address Register
(HW_APBH_CH4_CURCMDAR)
APBH DMA Channel 4 Next Command Address Register
(HW_APBH_CH4_NXTCMDAR)
APBH DMA Channel 4 Command Register
(HW_APBH_CH4_CMD)
APBH DMA Channel 4 Buffer Address Register
(HW_APBH_CH4_BAR)
APBH DMA Channel 4 Semaphore Register
(HW_APBH_CH4_SEMA)
AHB to APBH DMA Channel 4 Debug Information
(HW_APBH_CH4_DEBUG1)
AHB to APBH DMA Channel 4 Debug Information
(HW_APBH_CH4_DEBUG2)
APBH DMA Channel 5 Current Command Address Register
(HW_APBH_CH5_CURCMDAR)
APBH DMA Channel 5 Next Command Address Register
(HW_APBH_CH5_NXTCMDAR)
APBH DMA Channel 5 Command Register
(HW_APBH_CH5_CMD)
APBH DMA Channel 5 Buffer Address Register
(HW_APBH_CH5_BAR)
APBH DMA Channel 5 Semaphore Register
(HW_APBH_CH5_SEMA)
AHB to APBH DMA Channel 5 Debug Information
(HW_APBH_CH5_DEBUG1)
AHB to APBH DMA Channel 5 Debug Information
(HW_APBH_CH5_DEBUG2)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBH memory map (continued)
Register name
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Freescale Semiconductor, Inc.
00A0_0000h
00A0_0000h
00A0_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
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6.5.32/400
6.5.33/400
6.5.34/401
6.5.35/403
6.5.36/404
6.5.37/405
6.5.38/405
6.5.39/407
6.5.40/408
6.5.41/409
6.5.42/411
6.5.43/412
6.5.44/412
6.5.45/413
6.5.46/415
6.5.47/416
6.5.48/417
6.5.49/419
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