MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 352

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Behavior During Reset
Note that each word of the three-word DMA command structure corresponds to a PIO
register of the DMA that is accessible on the APBH bus. Normally, the DMA copies the
next command structure onto these registers for processing at the start of each command
by following the value of the pointer previously loaded into the NEXTCMD_ADDR register.
To start DMA processing for the first command, initialize the PIO registers of the desired
channel, as follows:
6.4 Behavior During Reset
A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See
Correct Way to Soft Reset a Block
CLKGATE bit fields.
6.5 Programmable Registers
APBH Hardware Register Format Summary
352
8000_4000
8000_4010
8000_4020
8000_4030
8000_4040
8000_4050
8000_4060
Absolute
• First, load the next command address register with a pointer to the first command to
• Then, write 1 to the counting semaphore register. This causes the DMA to schedule the
address
(hex)
be loaded.
targeted channel for the DMA command structure load, as if it just finished its previous
command.
AHB to APBH Bridge Control and Status Register 0
(HW_APBH_CTRL0)
AHB to APBH Bridge Control and Status Register 1
(HW_APBH_CTRL1)
AHB to APBH Bridge Control and Status Register 2
(HW_APBH_CTRL2)
AHB to APBH Bridge Channel Register
(HW_APBH_CHANNEL_CTRL)
AHB to APBH DMA Device Assignment Register
(HW_APBH_DEVSEL)
AHB to APBH DMA burst size
(HW_APBH_DMA_BURST_SIZE)
AHB to APBH DMA Debug Register (HW_APBH_DEBUG)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_APBH memory map
for additional information on using the SFTRST and
(in bits)
Width
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
Freescale Semiconductor, Inc.
E000_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0055_5555h
0000_0000h
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6.5.7/371
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