MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1534

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
24.3.1 UART Data Register (HW_UARTDBG_DR)
Debug Uart Data Register. For words to be transmitted: 1) If the FIFOs are enabled, data
written to this location is pushed onto the transmit FIFO 2) If the FIFOs are not enabled,
data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
The write operation initiates transmission from the PrimeCell UART. The data is prefixed
with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop
bit. The resultant word is then transmitted. For received words: 1) If the FIFOs are enabled,
the data byte and the 4-bit status (break, frame, parity, and overrun) are pushed onto the
12-bit wide receive FIFO 2) If the FIFOs are not enabled, the data byte and status are stored
in the receiving holding register (the bottom word of the receive FIFO). The received data
byte is read by performing reads from the DR register along with the corresponding status
information. The status information can also be read by a read of the RSR_ECR register.
Address:
Re-
1534
set
Bit
W
R
8007_403C
8007_4038
8007_4040
8007_4044
8007_4048
UNAVAILABLE
Absolute
address
Reserved
31
(hex)
0
31 16
15 12
Field
OE
11
30
0
29
0
HW_UARTDBG_DR
UART Interrupt Mask Set/Clear Register
(HW_UARTDBG_IMSC)
UART Raw Interrupt Status Register (HW_UARTDBG_RIS)
UART Masked Interrupt Status Register (HW_UARTDBG_MIS)
UART Interrupt Clear Register (HW_UARTDBG_ICR)
UART DMA Control Register (HW_UARTDBG_DMACR)
28
0
The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are
always unavailable.
This bitfield is reserved.
Reserved.
Overrun Error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to
0 once there is an empty space in the FIFO and a new character can be written to it.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
UNAVAILABLE
25
0
24
0
HW_UARTDBG memory map (continued)
23
0
HW_UARTDBG_DR field descriptions
8007_4000h base + 0h offset = 8007_4000h
Register name
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
RESERVED
Description
14
0
13
0
12
0
(in bits)
Width
32
32
32
32
32
11
0
10
0
Access
0
9
R/W
R/W
R/W
R
R
0
8
Freescale Semiconductor, Inc.
0
7
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0
6
0
5
DATA
0
4
3
0
24.3.10/1542
24.3.11/1543
24.3.12/1545
24.3.13/1546
24.3.14/1547
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page
0
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