MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 862

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MCIMX281AVM4B

Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets

Specifications of MCIMX281AVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
Programmable Registers
10.8.5 System PLL2, Ethernet PLL Control Register 0
HW_CLKCTRL_PLL2CTRL0: 0x040
HW_CLKCTRL_PLL2CTRL0_SET: 0x044
HW_CLKCTRL_PLL2CTRL0_CLR: 0x048
HW_CLKCTRL_PLL2CTRL0_TOG: 0x04C
The System PLL2 Control Register 0 programs the Ethernet PLL.
EXAMPLE
HW_CLKCTRL_PLL2CTRL0_WR(BF_CLKCTRL_PLL2CTRL0_POWER(1));
PLL lock before using it
Address:
862
Reset
Reset
CLKGATE
Bit
Bit
LFR_SEL
W
W
RSRVD3
R
R
29 28
Field
31
30
31
15
1
0
(HW_CLKCTRL_PLL2CTRL0)
HW_CLKCTRL_PLL2CTRL0 8004_0000h base + 40h offset = 8004_0040h
30
14
0
0
PLL Clock Gate. If set to 1, the ENET PLL clock is off (power savings). 0: ENET PLL clock is enabled.
Always set to zero (0).
TEST MODE FOR FREESCALE USE ONLY. Adjusts loop filter resistor.
LFR_SEL
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CLKCTRL_PLL2CTRL0 field descriptions
28
12
0
0
27
11
0
0
26
10
0
0
25
CP_SEL
0
0
9
RSRVD1[15:0]
24
0
0
8
Description
23
0
0
7
22
// enable PLL and wait 10 us to let
0
0
6
21
0
5
0
20
RSRVD1[22:16]
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0

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