MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 500

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

APBX DMA
Thus, a single command structure can issue 32-bit PIO write operations to key registers in
the associated device using the same APB bus and the controls, it uses to write DMA data
bytes to the device. For example, this allows a chain of operations to be issued to the serial
audio interface to send command bytes, address bytes, and data transfers, where the command
and the address structure is completely under software control, but the administration of
that transfer is handled autonomously by the DMA.
Each DMA structure can have from 0 to 15 PIO words appended to it. The #PIOWORDs
field, if non-zero, instructs the DMA engine to copy these words to the APB, beginning at
PADDR = 0x0000 and incrementing its PADDR for each cycle. (Note that for APBX DMA
Channel 8, which is the UART RX channel, the first PIO word in the DMA command is
CTRL0. However, for APBX DMA Channel 9, which is the UART TX, the first PIO word
in a DMA command is CTRL1.)
The DMA master generates only normal read/write transfers to the APBX. It does not
generate set, clear, or toggle SCT transfers.
After any requested PIO words have been transferred to the peripheral, the DMA examines
the two-bit command field in the channel command structure. The following table shows
the four commands implemented by the DMA.
500
COMMAND
DMA
00
01
Figure 7-2. AHB-to-APBX Bridge DMA Channel Command Structure
word 3-n
word 0
word 2
word 1
NO_DMA_XFER. Perform any requested PIO word transfers, but terminate the command before any DMA
transfer.
DMA_WRITE. Perform any requested PIO word transfers, and then perform a DMA transfer from the peri-
pheral for the specified number of bytes.
Usage
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 7-2. APBX DMA Commands
XFER_COUNT
BUFFER ADDRESS
PIOWORD Value
NEXTCMDADDR
Freescale Semiconductor, Inc.