MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2216

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
35.3.2 SAIF Status Register (HW_SAIF_STAT)
The SAIF Status Register provides status of key hardware components required by software
of the SAIF module.
HW_SAIF_STAT: 0x010
HW_SAIF_STAT_SET: 0x014
HW_SAIF_STAT_CLR: 0x018
HW_SAIF_STAT_TOG: 0x01C
The SAIF Status Register provides the status of interrupt requests and active operation of
the SAIF.
EXAMPLE
unsigned TestBit = HW_SAIF_STAT.PRESENT;
2216
READ_MODE
Field
RUN
1
0
codec. When SLAVE_MODE=0, both BITCLK and LRCLK start to transition immediately after the RUN bit
is set. Note that when in transmit mode or receive master mode, the user must configure the SAIF's clock
controls within the clock controller to the correct oversample rate (see
BITCLK_BASE_RATE/BITCLK_MULT_RATE above).
0 = Master mode. SAIF drives BITCLK and LRCLK
1 = Slave mode. SAIF uses BITCLK and LRCLK as inputs to determine when to sample input PCM data.
Note that is bit is ignored in transmit operation (READ_MODE=0).
SAIF Transmit/Receive Select. This bit selects whether the SAIF block transmits to an off-chip DAC (write
mode) or receives from an off-chip ADC (read mode). The selected mode (TX or RX) starts operation once
the RUN bit is set.
0 = TX or write mode
1 = RX or read mode
Setting this bit to one causes the SAIF to begin transmitting or receiving serial PCM data, depending on the
programming of the READ_MODE bit. For transmit, when this bit is cleared, operation ends after transmission
of the current active channel set (pairs from all enabled channels) from the FIFO. If the FIFO is already
empty and the RUN bit is cleared, operation halts immediately and the LRCLK and BITCLK pins stop
transitioning. For receive, when the RUN bit is cleared, reception ends after the current active channel set
(pairs from all enabled channels) are pushed to the FIFO. Note for 4- and 6-channel operation, clearing the
RUN bit means that the SAIF does not stop until the corresponding audio samples for all 4 or 6 channels
have been transmitted or received.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SAIF_CTRL field descriptions (continued)
Description
Freescale Semiconductor, Inc.