MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1584

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
Address:
Re-
25.6.6 Rx 15 Mask (HW_CAN_RX15MASK)
The default value of this register is 0xffffffff.
When the BCC bit is cleared, RX15MASK is used as acceptance mask for the identifier in
message buffer 15. When the FEN bit in the MCR is set (FIFO enabled), the RXG14MASK
also applies to element 7 of the ID filter table. Setting the BCC bit in the MCR causes the
RX15MASK register to have no effect on the module operation. This register has the same
structure as the RXGMASK. It must be programmed while the module is in freeze mode,
and must not be modified when the module is transmitting or receiving frames.
Address:
Re-
25.6.7 Error Counter Register (HW_CAN_ECR)
This register has two 8-bit fields which reflect the value of the transmit error counter
(tx_err_counter field) and receive error counter (rx_err_counter field).
1584
set
set
Bit
Bit
W
W
R
R
31
31
1
1
Field
31 0
Field
31 0
MI
MI
30
30
1
1
29
29
1
1
HW_CAN_RX14MASK
HW_CAN_RX15MASK
28
28
1
1
This register is provided for legacy support and for low cost MCUs that do not have the individual masking
per message buffer feature.
This register is provided for legacy support and for low cost MCUs that do not have the individual masking
per message buffer feature.
27
27
1
1
26
26
1
1
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
1
1
24
24
1
1
HW_CAN_RX14MASK field descriptions
HW_CAN_RX15MASK field descriptions
23
23
1
1
22
22
1
1
8003_2000h base + 14h offset = 8003_2014h
8003_2000h base + 18h offset = 8003_2018h
21
21
1
1
20
20
1
1
19
19
1
1
18
18
1
1
17
17
1
1
16
16
1
1
MI
MI
15
15
1
1
Description
Description
14
14
1
1
13
13
1
1
12
12
1
1
11
11
1
1
10
10
1
1
1
1
9
9
1
1
8
8
Freescale Semiconductor, Inc.
1
1
7
7
1
1
6
6
1
1
5
5
1
1
4
4
3
1
3
1
1
1
2
2
1
1
1
1
1
1
0
0