MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1602

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Unified DMA Block Guide
26.2.2.31.1.5
MAC error. This bit is written by the uDMA. This bit means that the frame stored in the
system memory was received with an error. This bit is only valid when the L-bit is set.
26.2.2.31.1.6
a DMA detects an error during the data transfer.
26.2.2.31.1.7
PHY Error. This bit is written by the uDMA. Set to 1 when the frame was received with an
Error character on the PHY interface. The frame is invalid. This bit is valid only when the
L-bit is set.
26.2.2.31.1.8
Collision. This bit is written by the uDMA. Set to 1 when the frame was received with a
collision detected during reception. The frame is invalid and sent to the user application.
This bit is valid only when the L-bit is set.
26.2.2.31.1.9
Unicast. This bit is written by the uDMA. This bit means that the frame is unicast. This bit
is valid regardless of if the L-bit is set.
26.2.2.31.1.10
that the uDMA is to generate an interrupt on the dma_int_rxb / dma_int_rxf event.
26.2.2.31.1.11
IP header checksum error. This is an accelerator option. This bit is written by the uDMA.
Set to 1 when either not an IP frame is received, or the IP header checksum was invalid.
This bit is only valid if the L-bit is set.
26.2.2.31.1.12
Protocol checksum error. This is an accelerator option. This bit is written by the uDMA.
Set to 1 when the checksum of the protocol is invalid, or an unknown protocol is found and
checksumming could not be performed. This bit is only valid if the L-bit is set.
26.2.2.31.1.13
Type removed. This is an accelerator option. This bit is written by the uDMA. If set, this
bit indicates that the frame's type feld has been removed: The frames payload starts
immediately after the MAC source address within the frame, or after the VLAN tag if
present. This bit is only valid if the L-bit is set. The date for this bit comes from the MTIP
sideband signal ff_rx_ip_stat[7].
1602
Offset + 8 Bit 15 ME
Offset + 8 Bit 14
This bit is not used (reserved) since the uDMA aborts the operation when
Offset + 8 Bit 10 PE
Offset + 8 – Bit 9 CE
Offset + 8 – Bit 8 UC
Offset + 8 – Bit 7 INT
Generate RXB/RXF interrupt. This bit is set by the user. This bit indicates
Offset + A – Bit 5 ICE
Offset + A – Bit 4 PCR
Offset + A – Bit 3
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.