MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1583

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

25.6.4 Rx Global Mask (HW_CAN_RXGMASK)
The default value of this register is 0xffffffff.
This register is provided for legacy support and for low cost MCUs that do not have the
individual masking per message buffer feature. For MCUs supporting individual masks per
message buffer, setting the BCC bit in the MCR causes the RXGMASK register to have no
effect on the module operation. For MCUs not supporting individual masks per message
buffer, this register is always effective. RXGMASK is used as acceptance mask for all Rx
message buffers, excluding message buffers 14C15, which have individual mask registers.
When the FEN bit in the MCR is set (FIFO enabled), the RXGMASK also applies to all
elements of the ID filter table, except elements 6-7, which have individual masks. Setting
the BCC bit in MCR causes the RXGMASK register to have no effect on the modules
operation. The contents of this register must be programmed while the module is in freeze
mode, and must not be modified when the module is transmitting or receiving frames.
Address:
Re-
25.6.5 Rx 14 Mask (HW_CAN_RX14MASK)
The default value of this register is 0xffffffff.
RX14MASK is used as acceptance mask for the identifier in message buffer 14. When the
FEN bit in the MCR is set (FIFO enabled), the RXG14MASK also applies to element 6 of
the ID filter table. Setting the BCC bit in the MCR causes the RX14MASK register to have
no effect on the module operation. This register has the same structure as RXGMASK. It
must be programmed while the module is in freeze mode, and must not be modified when
the module is transmitting or receiving frames.
Freescale Semiconductor, Inc.
set
Bit
W
R
31
1
Field
31 0
MI
30
1
29
1
HW_CAN_RXGMASK
28
1
This register is provided for legacy support and for low cost MCUs that do not have the individual masking
per message buffer feature.
27
1
26
1
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
1
24
1
HW_CAN_RXGMASK field descriptions
23
1
22
1
8003_2000h base + 10h offset = 8003_2010h
21
1
20
1
19
1
18
1
17
1
16
1
MI
15
1
Description
14
1
13
1
Chapter 25 Controller Area Network (FlexCAN)
12
1
11
1
10
1
1
9
1
8
1
7
1
6
1
5
1
4
3
1
1
2
1
1
1583
1
0