MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1987

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

31.7.19 USB Interrupt Enable Register (HW_USBCTRL_USBINTR)
The interrupts to software are enabled with this register. An interrupt is generated when a
bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still
shows interrupt sources even if they are disabled by the USBINTR register, allowing polling
of interrupt events by the software.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
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W
R
R
RSVD5
31 26
Field
Field
TIE1
UEI
25
UI
1
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31
15
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HW_USBCTRL_USBINTR 8008_0000h base + 148h offset = 8008_0148h
30
14
0
0
USB Error Interrupt (USBERRINT).
When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller.
This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt
on complete (IOC) bit set. See Section 4.15.1 in the EHCI specification for a complete list of host error
interrupt conditions.
The device controller detects resume signaling only.
USB Interrupt (USBINT).
This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB
transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set.
This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when
the actual number of bytes received was less than the expected number of bytes.
Reserved.
General-Purpose Timer Interrupt Enable 1.
When this bit is a 1, and the GPTINT1 bit in the USBSTS register is a 1, the controller will issue an interrupt.
The interrupt is acknowledged by software clearing the GPTINT1 bit.
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HW_USBCTRL_USBSTS field descriptions (continued)
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RSVD5
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_USBCTRL_USBINTR field descriptions
28
12
0
0
27
11
0
0
26
10
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0
RSVD1
TIE1
25
0
0
9
Chapter 31 USB High-Speed On-the-Go Host Device Controller
TIE0
SLE
24
0
0
8
Description
Description
SRE
23
0
0
7
URE
22
0
0
6
RSVD4
AAE
21
0
5
0
SEE
20
0
4
0
UPIE
FRE
19
0
0
3
UAIE
PCE
18
0
0
2
RSVD3
UEE
17
0
0
1
UE
1987
16
0
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0