MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1156
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 1156 of 2327
- Download datasheet (17Mb)
Programmable Registers
Address:
Re-
14.8.54 DRAM Control Register 59 (HW_DRAM_CTL59)
This is a DRAM configuration register.
1156
set
Bit
W
R
INT_STATUS
INT_MASK
31
0
RSVD2
RSVD1
31 27
26 16
15 11
Field
10 0
30
0
RSVD2
29
0
HW_DRAM_CTL58
28
0
Always write zeroes to this field.
Status of interrupt features in the controller. READ-ONLY
Shows the status of all possible interrupts generated by the EMI. The MSB is the result of a logical OR of
all the lower bits. This parameter is read-only.
Backwards compatibility is available for register parameters across configurations. However, even with this
compatibility, the individual bits, their meaning and the size of the int_status parameter may change.
The int_status bits correspond to these interrupts:
Bit [10] = Logical OR of all lower bits.
Bit [9] = User-initiated DLL resync is finished.
Bit [8] = DLL lock state change condition detected. (i.e. lock to unlock or unlock to lock)
Bit [7] = Indicates that a read DQS gate error occurred.
Bit [6] = ODT enabled and CAS Latency 3 programmed error detected. This is an unsupported programming
option.
Bit [5] = Both DDR2 and Mobile modes have been enabled.
Bit [4] = DRAM initialization complete.
Bit [3] = Error was found with command data channel in a port.
Bit [2] = Error was found with command channel in a port.
Bit [1] = Multiple accesses outside the defined PHYSICAL memory space detected.
Bit [0] = A single access outside the defined PHYSICAL memory space detected.
Always write zeroes to this field.
Mask for controller_int signals from the INT_STATUS parameter.
Active-high mask bits that control the value of the EMI_int signal on the ASIC interface. Unless the user has
suppressed interrupt reporting (by setting bit [10] of this parameter to 'b1), bits [9:0] of the int_mask parameter
will be inverted and logically AND'ed with bits [9:0] of the int_status parameter and the result is reported on
the controller_int signal.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_DRAM_CTL58 field descriptions
INT_STATUS
800E_0000h base + E8h offset = 800E_00E8h
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
RSVD1
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
INT_MASK
0
6
0
5
0
4
3
0
0
2
0
1
0
0
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