MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2228

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
(B) Simpler Calculation:
Option A is ideal as it allows a lower floor frequency; option B can be used to keep it simple
and avoid confusion.
36.2.4 PIO Debug Mode
The block is connected only as a PIO device to the APBX bus. Even though it is designed
to work with the DMA controller integrated in the APBX bridge, all transfers to and from
the block are programmed I/O (PIO) read or write cycles. When the DMA is ready to write
to the HW_SPDIF_DATA register, it does so with standard APB write cycles. There are
four DMA related signals that connect the SPDIF transmitter to the DMA, but all data
transfers are standard PIO cycles on the APB. The state of these four signals can be seen
in the HW_SPDIF_DEBUG register.
Therefore, it is possible to completely exercise the SPDIF block for diagnostic purposes,
using only load and store instructions from the CPU without ever starting the DMA
controller. This section describes how to interact with the block using PIO operations, and
also defines the block's detailed behavior.
Whenever the HW_SPDIF_CTRL register is written to, by either the CPU or the DMA, it
establishes the basic operation mode for the block. If the HW_SPDIF_CTRL register is
written with a 1 in the RUN bit, then the operation begins and the SPDIF attempts to read
the data block by toggling its PDMAREQ signal to the DMA. Notice that the PDMAREQ
signal is defined as a toggle signal. This changes state to signify either a request for another
DMA word or a notification that the current command transfer has been ended by the SPDIF.
Diagnostic software should poll these signals to determine when the SPDIF is ready for
another DMA write, and can then supply data by storing a 32-bit word to the
HW_SPDIF_DATA register, just as the DMA would perform in a normal operation.
To perform SPDIF transfers in PIO debug mode, diagnostic software should perform the
following:
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1. Clear CLKGATE in the HW_CLKCTRL_SPDIF register.
2. Turn off the Soft Reset bit, HW_SPDIF_CTRL_SFTRST, and the Clock Gate bit,
HW_SPDIF_CTRL_CLKGATE.
min freq = [2*(DMA latency+4) + 7] * sample rate.
For max DMA latency = 24 cycles and max SPDIF sample rate = 96 kHz,
min APBX freq = 6.048 MHz.
Floor APBX freq = 2*(latency + 9) * sample rate = twice that of 16-bit mode.
For max latency = 24 cycles and max sample rate = 96 kHz,
min APBX freq = 6.336 MHz.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.