MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1483

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits
4,294,967,294 milliseconds or 49.7 days before it must deal with a counter wrap. The
programmer can change the resolution of the millisecond counter to be 1, 2, 4, 8, or 16
milliseconds. This is programmed through bits in Persistent Register 0.
CAUTION: When the 32.768-KHz or 32.000-KHz crystal oscillator is selected as the
source for the seconds counter, an anomaly is created between the time intervals of the
millisecond counter and the seconds counter. That is, the manufacturing tolerance of the
two crystals are such that 1000 millisecond counter increments are not exactly one second
as measured by the real-time clock seconds counter.
22.6 Alarm Clock Function
The alarm clock function allows an application to specify a future instant at which the chip
should be awakened, that is, if powered down, it can be powered up. The alarm clock setting
is a CPU-accessible, 32-bit value that is continuously matched against the 32-bit real-time
clock seconds counter. When the two values are equal, an alarm event is triggered. Persistent
bits indicate whether an alarm event should power up the chip from its powered-down state.
In addition to or instead of powering up the chip, the alarm event can also cause a CPU
interrupt. Although these two functions can be enabled at the same time, one should
remember that the CPU will only be interrupted if the chip is powered up at the time of the
alarm event.
NOTE: If the alarm is set to power up the chip in the event of an alarm and such an event
occurs, then the only record of the cause of the wake-up is located in the analog side. At
power-up, the analog side registers are copied to the digital shadow registers and the
ALARM_WAKE bit in the Persistent register 0 is visible in the digital shadow register. If
an alarm wake event occurs while the chip is powered up, the ALARM_WAKE bit will not
be set in the persistent register because the chip was not woken up.
The alarm must be present on an actual chip to perform this function (see the
HW_RTC_STAT_ALARM_PRESENT bit description).
22.7 Watchdog Reset Function
The watchdog reset is a CPU-configurable device. It is programmed by software to generate
a chip-wide reset after HW_RTC_WATCHDOG milliseconds. The watchdog generates
this reset if software does not rewrite this register before this time elapses.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1483