MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2267

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

38.3 Channel Threshold Detection
There are two identical threshold detection units implemented in the LRADC. They are
configured through the registers HW_LRADC_THRESHOLD0 and
HW_LRADC_THRESHOLD1. This functionality compares the sampled 18-bit value from
a LRADC channel against a programmed threshold value. It can be programmed to do this
comparison in two ways. First, it will detect when the sampled channel value crosses from
above the threshold value down to equal or less than that value. Conversely, it can also be
set up to detect when the sampled channel value changes from below to equal to or above
the threshold value.
When the programmed crossing is detected, the
HW_LRADC_CTRL1_THRESHOLDx_DETECT_IRQ interrupt register bits will assert.
These bits can be interrupt sources back to the CPU if enabled through the
HW_LRADC_CTRL1_THRESHOLDx_DETECT_IRQ_EN bits. The interrupt bits must
be cleared before another threshold crossing can be detected. Any one of the eight virtual
channels can be mapped to either or both of the threshold detection units. Note that the
threshold event can occur on the very first channel conversion after the threshold unit is
enable. For example, consider the case where a threshold unit was programmed for
DETECT_HIGH and enabled. If the connected channel was then converted and the value
was equal or greater than the threshold value this would satisfy the threshold requirement
and the event would be logged by setting the IRQ bit. However, after this first conversion,
a threshold event will only be tripped again on subsequent conversions if the value drops
below the threshold and then crosses it again. In other words, if the channel value remains
above the threshold on multiple sequential conversions, the threshold event will be logged
only once (after the first conversion in the sequence that tripped the threshold).
Either threshold unit can be used to disable the battery charger when a threshold event
occurs. This functionality is enabled by setting the
HW_LRADC_THRESHOLDx_BATTCHRG_DISABLE bit. When enabled, and the
threshold is tripped, the HW_POWER_CHARGE0_ PWD_BATTCHRG bit will set. This
is an event that is triggered once when the conditions are met (PWD_BATTCHRG is not
Freescale Semiconductor, Inc.
If a delay group schedules channels to be sampled and a manual
write to the schedule field in CTRL0 occurs while the block is
discarding samples, the LRADC will switch to the new schedule
and will not sample the channels that were previously scheduled.
The time window for this to happen is very small and lasts only
while the LRADC is discarding samples.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface
Note
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