MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2203

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

For codecs that do not contain their own PLL, or in applications where including a crystal
oscillator to drive the codec is not desired, the SAIF can provide a master clock (MCLK)
reference that can be configured from 512x down to 32x the audio data's sample rate. This
master clock is used by the off-chip codec for all of its internal logic and to synchronize
the BITCLK/LRCLK/SDATA inputs for DAC operation.
The digital PCM audio sample rate is determined by programming a fractional divider
within the clock controller module.
35.2.1 Sample Rate Programming and Codec Clocking Operation
SAIF clocking is programmed in three blocks of the device:
The saif_clk (shown in
fractional divider that divides down the 480 MHz PLL reference. The fractional divider
minimizes system cost and power by eliminating the need for a second on-chip PLL. This
fractional divider continuously selects which edge of the PLL reference clock (positive or
negative) to use to best represent the oversample rate, such that less than 2 ns of correlated
jitter occurs in saif_clk (jitter of the PLL plus periodic jitter of the fractional divide). This
low level of jitter is required by most codec manufacturers to ensure a high SNR.
Table 35-1
standard sample rates with either a base oversample rate of 512 or 384 times the sample
rate.
These two base oversample values are the base rates typically required by codecs for the
master clock (MCLK). An additional divider exists within the SAIF to generate sub-multiples
of these two base rates if MCLK is required by the codec.
The 384xFs base rate is common among systems that include MPEG1/2/4 audio and video,
and AAC and AC-3 (Dolby Digital) audio. These MCLK rates are generated by programming
the HW_SAIF_CTRL_BITCLK_BASE_RATE and
HW_SAIF_CTRL_BITCLK_MULT_RATE bit fields.
Freescale Semiconductor, Inc.
• Clock control module (CLKCTRL)
• SAIF module
• Digital control module (DIGCTL)
• The sub-rates that can be generated from 512x are: 256x, 128x, 64x, and 32x.
• The sub-rates for the 384x base rate are: 192x, 96x, and 48x.
shows the values to program the HW_CLKCTRL_SAIF_DIV bit field for all
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure
35-1) is generated by the CLKCTRL block with a 16-bit
Chapter 35 Serial Audio Interface (SAIF)
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