MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 195
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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5.4.38 Interrupt Collector Interrupt Register 28
This register provides a mechanism to specify the priority level for an interrupt source. It
also provides an enable and software interrupt for each one, as well as security designation.
HW_ICOLL_INTERRUPT28: 0x2E0
HW_ICOLL_INTERRUPT28_SET: 0x2E4
HW_ICOLL_INTERRUPT28_CLR: 0x2E8
HW_ICOLL_INTERRUPT28_TOG: 0x2EC
This register provides a mechanism to specify the priority associated with an interrupt bit.
In addition, this register controls the enable and software generated interrupt. WARNING:
Modifying the priority of an enabled interrupt may result in undefined behavior. You should
always disable an interrupt prior to changing its priority.
EXAMPLE
HW_ICOLL_INTERRUPT28_SET(0,0x00000001);
Address:
Freescale Semiconductor, Inc.
Reset
PRIORITY
Bit
W
R
Field
1 0
31
0
(HW_ICOLL_INTERRUPT28)
HW_ICOLL_INTERRUPT28
02E0h
30
0
Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest).
0x0
0x1
0x2
0x3
HW_ICOLL_INTERRUPT27 field descriptions (continued)
29
0
LEVEL0 — level 0, lowest or weakest priority
LEVEL1 — level 1
LEVEL2 — level 2
LEVEL3 — level 3, highest or strongest priority
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
0
27
0
8000_0000h base + 2E0h offset = 8000_
26
0
25
0
RSRVD1[31:16]
24
0
Description
23
0
22
0
21
0
Chapter 5 Interrupt Collector (ICOLL)
20
0
19
0
18
0
17
0
16
0
195
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