MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1294

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
16.6.6 Hardware BCH ECC Loopback Metadata Buffer Register
When performing memory to memory operations, indicates the address of the metadata
buffer.
For memory to memory operations, this register is used as the pointer to the metadata to
encode or the extracted metadata for decode operations.
EXAMPLE
Address:
Re-
16.6.7 Hardware ECC Accelerator Layout Select Register
The BCH LAYOUTSELECT register provides a mapping of chip selects to layout registers.
When the BCH engine receives a request to process a data block from the GPMI interface,
it will use this register to map the incoming chip select to one of the four possible flash
layout registers
EXAMPLE
1294
set
Bit
W
R
31
0
ADDR
ADDR
Field
31 0
Field
31 0
30
0
29
0
(HW_BCH_METAPTR)
(HW_BCH_LAYOUTSELECT)
HW_BCH_METAPTR
28
0
Address pointer to data buffer. This is the source for encode operations and the destination for decode
operations. This register should be programmed before writing a 1 to the M2M_ENABLE bit in the CTRL
register. This value must be aligned on a 4 byte boundary.
Address pointer to metadata buffer.This is the source for encode metadata read operations and the destination
for metadata decode operations. This register should be programmed before writing a 1 to the M2M_ENABLE
bit in the CTRL register. This value must be aligned on a 4 byte boundary.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_BCH_METAPTR field descriptions
HW_BCH_DATAPTR field descriptions
22
8000_A000h base + 50h offset = 8000_A050h
0
21
0
20
0
19
0
18
0
17
0
ADDR
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0