MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1989

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

31.7.20 USB Frame Index Register (HW_USBCTRL_FRINDEX)
This register is used by the host controller to index the periodic frame list. The register
updates every 125 microseconds (once each micro-frame). Bits [N: 3] are used to select a
particular entry in the Periodic Frame List during periodic schedule execution. The number
of bits used for the index depends on the size of the frame list as set by system software in
the Frame List Size field in the USBCMD register. This register must be written as a DWord.
Byte writes produce-undefined results. This register cannot be written unless the Host
Controller is in the 'Halted' state as indicated by the HCHalted bit. A write to this register
while the Run/Stop bit is set to a 1 produces undefined results. Writes to this register also
affect the SOF value. In device mode this register is Read-Only and, the device controller
updates the FRINDEX [13:3] register from the frame number indicated by the SOF marker.
Whenever a SOF is received by the USB bus, FRINDEX [13:3] will be checked against the
SOF marker. If FRINDEX [13:3] is different from the SOF marker, FRINDEX [13:3] will
be set to the SOF value and FRINDEX [2:0] will be set to 0 (i.e., SOF for 1 ms frame). If
FRINDEX [13:3] is equal to the SOF value, FRINDEX [2:0] will be incremented (i.e., SOF
for 125 us micro-frame.) * The default value of this register is undefined (free-running
counter).
Freescale Semiconductor, Inc.
Field
SEE
FRE
PCE
UEE
UE
4
3
2
1
0
System Error Enable.
When this bit is a 1, and the System Error bit in the USBSTS register is a 1, the host/device controller will
issue an interrupt. The interrupt is acknowledged by software clearing the System Error bit.
Frame List Rollover Enable.
When this bit is a 1, and the Frame List Rollover bit in the USBSTS register is a 1, the host controller will
issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. Only used
by the host controller.
Port Change Detect Enable.
When this bit is a 1, and the Port Change Detect bit in the USBSTS register is a 1, the host/device controller
will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit.
USB Error Interrupt Enable.
When this bit is a 1, and the USBERRINT bit in the USBSTS register is a 1, the host controller will issue an
interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT
bit in the USBSTS register.
USB Interrupt Enable.
When this bit is a 1, and the USBINT bit in the USBSTS register is a 1, the host/device controller will issue
an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT
bit.
HW_USBCTRL_USBINTR field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 31 USB High-Speed On-the-Go Host Device Controller
Description
1989