MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1145

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Address:
Re-
14.8.39 DRAM Control Register 41 (HW_DRAM_CTL41)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
TRCD_INT
31
31
0
0
RSVD1
TPDEX
RSVD1
RSVD1
31 29
28 24
TMRD
31 16
TINIT
Field
23 0
Field
15 8
TRC
7 6
5 0
30
30
0
0
29
29
0
0
HW_DRAM_CTL40
HW_DRAM_CTL41
28
28
0
0
Always write zeroes to this field.
DRAM TMRD parameter in cycles.
Defines the minimum number of cycles required between two mode register write commands. This is the
time required to complete the write operation to the mode register.
DRAM TINIT parameter in cycles.
Defines the DRAM initialization time, in cycles.
DRAM TPDEX parameter in cycles.
Defines the DRAM power-down exit command period, in cycles.
DRAM TRCD parameter in cycles.
Defines the DRAM RAS to CAS delay, in cycles.
Always write zeroes to this field.
DRAM TRC parameter in cycles.
Defines the DRAM period between active commands for the same bank, in cycles.
27
27
0
0
TMRD
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
TPDEX
24
24
0
0
23
23
0
0
HW_DRAM_CTL40 field descriptions
HW_DRAM_CTL41 field descriptions
800E_0000h base + A0h offset = 800E_00A0h
800E_0000h base + A4h offset = 800E_00A4h
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
TRCD_INT
12
12
TINIT
0
0
Chapter 14 External Memory Interface (EMI)
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
RSVD1
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
TRC
0
0
2
2
0
0
1
1
1145
0
0
0
0