MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1713

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

26.4.88 ENET MAC IEEE1588 Timer Control Register
Note: The command bits can be used to trigger the corresponding events directly. It is not
necessary to preserve any of the configuration bits when a command bit is set in the register
(i.e. no read-modify-write is required). The bits read out 0 after the command has completed.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
FRC_SLAVE
CAPTURE
Bit
Bit
W
W
RSRVD0
RSRVD1
RSRVD2
R
R
31 14
Field
13
12
11
10
31
15
RSRVD0
0
0
[15:14]
HW_ENET_MAC_ATIME_CTRL 800F_0000h base + 400h offset = 800F_
0400h
(HW_ENET_MAC_ATIME_CTRL)
30
14
0
0
Reserved bits. Write as 0.
Enable timer slave mode. If set '1' the internal timer is disabled and instead the externally provided timer
value from pins frc_in() is used.
When operating in slave mode all other configuration bits in this register have no effect. Only the capture
command bit can still be used to capture the current timer value.
When disabled (0, default) the timer is active and all configuration bits in this register are relevant.
Reserved bits. Write as 0.
Capture timer value. When set the current time is captured and can be read from the ATIMER register.
Command bit: When set, all other bits are ignored during a write.
Reserved bits. Write as 0.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ENET_MAC_ATIME_CTRL field descriptions
28
12
0
0
27
11
0
0
26
10
0
0
25
0
0
9
RSRVD0[31:16]
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
Chapter 26 Ethernet Controller (ENET)
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
1713
16
0
0
0