MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1367

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

19.4.4 On-Chip RAM Control Register (HW_DIGCTL_RAMCTRL)
The On-Chip RAM Control Register holds on-chip SRAM control bit fields. This register
controls various parts of the on-chip RAM, including the speed select configuration.
HW_DIGCTL_RAMCTRL: 0x030
HW_DIGCTL_RAMCTRL_SET: 0x034
HW_DIGCTL_RAMCTRL_CLR: 0x038
HW_DIGCTL_RAMCTRL_TOG: 0x03C
EXAMPLE
Address:
Freescale Semiconductor, Inc.
Reset
Reset
DEBUG_ENABLE
machine
DEBUG_CODE
Bit
Bit
W
W
R
R
RSVD2
RSVD1
31 15
Field
12 8
RSVD2
[15:15]
14
13
31
15
0
0
HW_DIGCTL_RAMCTRL_SET(BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT);
HW_DIGCTL_RAMCTRL
30
14
0
0
Reserved.
Reserved, always set to zero.
Debug enable for on chip sram. Set DEBUG_CODE field for different debug mode.
Debug code for 8x32 OCRAM instances. Recommended value is 0x0. Used to change different data access
time. These bits are ignored if debug enable is low.
0x0
0x4
0x5
29
13
0
0
NORMAL — Normal functional mode.
DELAY1 — Normal functional mode.
DELAY2 — Normal functional mode.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_DIGCTL_RAMCTRL field descriptions
27
11
0
0
DEBUG_CODE
8001_C000h base + 30h offset = 8001_C030h
26
10
0
0
25
0
0
9
RSVD2[31:16]
24
0
0
8
Description
Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
RSVD0
// Start the efuse state
19
0
0
3
18
0
0
2
17
0
0
1
1367
16
0
0
0