MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1363

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor, Inc.
SAIF_LOOPBACK
DEBUG_DISABLE
USB1_CLKGATE
SAIF_CLKMUX_
TESTMODE
TESTMODE
LOOPBACK
LOOPBACK
AUART01_
ANALOG_
DIGITAL_
DUART_
RSVD1
RSVD0
11 10
Field
SEL
9 4
18
17
16
15
14
13
12
3
Set this bit to get into analog test mode
Set this bit to get into digital test mode
This bit must be cleared to 0 for normal operation of the USB controller. When set to 1, it gates off the
clocks to the USB controller. USB_CLKGATE can be set during suspend to gate the USB clock during
suspend. If this is gated, then the USB controller Reset Received bit (HW_USBCTRL_USBSTS_URI)
should be not be polled for reset during suspend; use the HW_USBPHY_CTRL_RESUME_IRQ bit instead.
This bit can be hardware auto cleared when wakeup from suspend happens
0x0
0x1
Set this bit to one to loop SAIF0 to SAIF1 and SAIF1 to SAIF0. To use SAIF loopback the user must
configure one SAIF for transmit and the other for receive. Because this bit connects SAIF0's output to
SAIF1's input, and SAIF1's output to SAIF0's input it doesn't matter which of the two ports is configured for
TX and the other for RX, either configuration will produce an internal TX to RX loopback.
0x0
0x1
Set this bit to one to loop the debug UART's RX and TX signals back on themselves in a null modem
configuration.
0x0
0x1
Set this bit to one to loop application UARTs 0 and 1 back on themselves in a null modem configuration.
0x0
0x1
Reserved.
Selects the source of the SAIF0 and SAIF1 input bit clock (BITCLK), and input left/right sample clock
(LRCLK).
0x0
0x1
0x2
0x3
Reserved.
Set this bit to disable the ARM core's debug logic (for power savings). This bit must remain 0 following
power-on reset for normal JTAG debugger operation of the ARM core. When set to 1, it gates off the clocks
to the ARM core's debug logic. Once this bit is set, the part must undergo a power-on reset to re-enable
debug operation. Manually clearing this bit through a write after it has been set produces unknown results.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RUN — Allow USB to operate normally.
NO_CLKS — Do not clock USB gates in order to minimize power consumption.
NORMAL — No loopback.
LOOPIT — Loop SAIF0 and SAIF1 back to each other.
NORMAL — No loopback.
LOOPIT — Loop debug UART TX and RX together.
NORMAL — No loopback.
LOOPIT — Loop application UART 0 and 1 together.
DIRECT — SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1 clock pins selected for
SAIF1 input clocks.
CROSSINPUT — SAIF1 clock inputs selected for SAIF0 input clocks, and SAIF0 clock inputs selected
for SAIF1 input clocks. This is the cross input mode.
CLKSRCSAIF0PIN — SAIF0 clock pin selected for both SAIF0 and SAIF1 input clocks.
CLKSRCSAIF1PIN — SAIF1 clock pin selected for both SAIF0 and SAIF1 input clocks.
HW_DIGCTL_CTRL field descriptions (continued)
Description
Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
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