MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1451

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

20.4.29 Shadow Register for OTP Bank3 Word2 (ROM Use 2)
Copied from the OTP automatically after reset. Can be re-loaded by setting
HW_OCOTP_CTRL[RELOAD_SHADOWS].
Shadowed memory mapped access to OTP Bank 3, word 2 (ADDR = 0x1A).
Freescale Semiconductor, Inc.
SD_INCREASE_
INIT_SEQ_TIME
SD_INIT_SEQ_
SD_INIT_SEQ_
NUMBER_OF_
SSP0_EXT_
SD_CMD0_
1_DISABLE
2_ENABLE
SEARCH_
SEARCH_
DISABLE
RSRVD1
RSRVD0
PULLUP
STRIDE
COUNT
NANDS
BOOT_
BOOT_
Field
11 8
7 4
2 0
17
16
15
14
13
12
3
(HW_OCOTP_ROM2)
Blow to indicate external pull-ups implemented for SSP0.
Blow to increase the SD card initialization sequence time from 1ms (default) to 4ms.
Blow to enable the second initialization sequence for SD boot.
Cmd0 (reset cmd) is called by default to reset the SD card during startup. Blow this bit to not reset the card
during SD boot.
Blow to disable the first initialization sequence for SD.
Reserved - do not blow these bits.
Number of 64 page blocks that should be read by the boot loader.
the value of these bits is multiplied by 64 to get boot search stride. The default is 1 boot search stride, i.e.
64 pages.
Reserved - do not blow these bits.
Encoded value indicates number of external NAND devices (0 to 7). Zero indicates ROM will probe for the
number of NAND devices connected in the system.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_OCOTP_ROM1 field descriptions (continued)
Description
Chapter 20 On-Chip OTP (OCOTP) Controller
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