MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1231

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

14.8.172 DRAM Control Register 183 (HW_DRAM_CTL183)
This is a DRAM configuration register.
Address:
Freescale Semiconductor, Inc.
Reset
MR0_DATA_2
Bit
W
R
RSVD1
Field
14 0
15
RSVD2
31
0
HW_DRAM_CTL183
30
0
should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state
machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and
therefore the bits A2:A0 should be set to 'b010.
For LPDDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared
to 'b0. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010.
This data will be programmed into the memory register of the DRAM at initialization or when the write_modereg
parameter is set to 'b1.
Always write zeroes to this field.
MRS data to program to memory mode register 0 for chip select 2.
Holds the memory mode register 0 data for chip select X written during memory initialization. Consult the
memory specification for the fields of this mode register.
This parameter correlates to the memory mode register (MR). The use of this parameter varies based on
the memory type connected to this EMI:
For DDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to
'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL
Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0
should be set to 'b010.For DDR2 memories: The EMI does not support interleaving and therefore the A3 bit
should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state
machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and
therefore the bits A2:A0 should be set to 'b010.
For LPDDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared
to 'b0. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010.
This data will be programmed into the memory register of the DRAM at initialization or when the write_modereg
parameter is set to 'b1.
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL182 field descriptions (continued)
28
0
800E_0000h base + 2DCh offset = 800E_02DCh
27
0
26
0
25
0
24
0
MR1_DATA_1
Description
23
0
22
0
Chapter 14 External Memory Interface (EMI)
21
0
20
0
19
0
18
0
17
0
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16
0