MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1445
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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20.4.23 Value of OTP Bank2 Word4 (Freescale OPS3)
OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading
this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN]
set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR]
being set and 0xBADA_BADA being returned.
Shadowed memory mapped access to OTP Bank 2, word 4 (ADDR = 0x14).
Address:
Re-
20.4.24 Value of OTP Bank2 Word5 (Unassigned0) (HW_OCOTP_UN0)
OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading
this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN]
set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR]
being set and 0xBADA_BADA being returned.
Non-shadowed memory mapped access to OTP Bank 2, word 5 (ADDR = 0x15).
Freescale Semiconductor, Inc.
set
Bit
W
R
31
0
Field
31 0
BITS
Field
31 0
BITS
30
0
29
0
HW_OCOTP_OPS3
(HW_OCOTP_OPS3)
28
0
Reflects value of OTP Bank 2, word 3 (ADDR = 0x13)
Reflects value of OTP Bank 2, word 4 (ADDR = 0x14), it is used to form the least significant bits of the unique
key.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_OCOTP_OPS2 field descriptions
HW_OCOTP_OPS3 field descriptions
8002_C000h base + 160h offset = 8002_C160h
22
0
21
0
20
0
19
0
18
0
17
0
16
0
BITS
15
0
Description
Description
14
0
13
0
12
0
Chapter 20 On-Chip OTP (OCOTP) Controller
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1445
0
0
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